Many circuits use phase lock loops to generate frequency signals. In an integer-N phase lock loop architecture (such as described below in conjunction with FIG. 1), the phase lock loop includes a phase frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO), which are connected in series to provide the frequency signal. The frequency signal is fed back through an integer divider to provide a feedback signal to the phase frequency detector. Such architecture has small reference spurs but has course frequency resolution and a long frequency locking time. For some applications, (e.g., wireless communication standards), such an architecture is inflexible.
A fractional-N phase lock loop architecture (such as described below in conjunction with FIG. 3) is similar to the integer-N phase lock loop architecture but includes a fractional divider between the VCO and the phase frequency detector. The fractional divider provides multiple integer dividers that vary so that the average divider may be fractional. Such architecture provides fast locking and fine frequency resolution, but provides fractional spurs due to the varying excess division. The fractional spurs from the charge pump have a larger spike than the integer N phase lock loop architecture.
A Delta-sigma fractional-N phase lock loop architecture (such as described below in conjunction with FIG. 5) is similar to the fractional-N architecture but further includes a delta-sigma modulator for modulating the fractional divider. The delta-sigma modulator receives a select signal R having k number of bits to provide a division ratio of N+R/2k. The high frequency spurs from the charge pump are filtered by the loop filter. The spurs from the charge pump have varying pulse widths, both positive and negative, which appear as noise. The Delta-sigma modulator may be, for example, third order.
In prior art systems, the spurious spurs can also be cancelled at the output of the charge pump by adding an error signal having a fixed pulse width with amplitude controlled by a digital to analog converter. However, the amplitude mismatch in a high resolution DAC severely degrades the performance of the phase lock loop. Using dynamic element matching to reshape such amplitude mismatch to higher frequency can reduce the in-band phase noise. However, it requires additional digital signal processing hardware and complicates DAC design.